AC ELECTRICAL CHARACTERISTICS (continued)

4. 0 M H z

5. 0 MH z

Number

Parameter

Min.

Max.

Min.

Max.

Unit

Notes

40

CS HIGH TO DATA Out High Impedence

120

90

ns

41

CS or IACK High to CLK Low

100

100

ns

7

42

TxRDY or RxRDY Width Low

3

3

CLK’s

8, 10

43

CLK High TxRDY or RxRDY Low

300

300

ns

44

CLK High to TxRDY or RxRDY High

300

300

ns

IACK High to CS Low or CS High to IACK Low

(not shown)

50

50

ns

1

45

CTS, DCD, SYNC Pulse Width High

200

200

ns

46

CTS, DCD, SYNC Pulse Width Low

200

200

ns

47

TxC Period

1000

DC

800

DC

ns

9

48

TxC Width Low

180

DC

180

DC

ns

49

TxC Width High

180

DC

180

DC

ns

50

TxC Low to TxD Delay (X1 Mode)

300

300

ns

51

TxC Low to INTR Low Delay

5

9

5

9

CLK’s

10

52

RxC Period

1000

DC

800

DC

ns

9

53

RxC Width Low

180

DC

180

DC

ns

54

RxC Width High

180

DC

180

DC

ns

55

RxD to RxC High Setup Time (X1 mode)

0

0

ns

56

RxC High to RxD Hold Time (X1 mode)

140

140

ns

57

RxC High to INTR Low Delay

10

13

10

13

CLK’s

10

58

RxC High to SYNC Low Delay (output modes)

4

7

4

7

CLK’s

10

59

RESET Low

1

1

CLK

10

60

XTAL 1 Width High (TTL in)

100

80

ns

61

XTAL 1 Width Low (TTL in)

100

80

ns

62

XTAL 1 Period (TTL in)

250

2000

200

2000

ns

63

XTAL 1 Period (crystal in)

250

1000

200

1000

ns

Not es : 1. This specification only applies if the SIO has completed all operations initiated by the previous bus cycle, when CS

or IACK was asserted. Following a read, write, or interrupt acknoledge cycle, all operations are complete within two

CLK cycles after the rising edge of CS or IACK. If CS or IACK is asserted prior to the completion of the internal

operations, the new bus cycle will be postponed.

2. If IEI meets the setup time to the falling edge of CLK, 1 1/2 cycles following the clocking in of IACK.

3. No internal interrupt request pending at the start of an interrupt acknoledge cycle.

4. Time starts when first signal goes invalid (high).

5. If an internal interrupt is pending at the end of the interrupt acknoledge cycle.

6. If Note 2 timing is not met.

7. If this spec is met, the delay listed in Note 1 will be one CLK cycle instead of two.

8. Ready signals will be negated asynchronous to the CLK, if the conditi on causing the assertion of the signals is

cleared.

9. If RxC and TxC are asynchronous to the System Clock, the maximum clock rate into RxC and TxC should be no

more than one-fifth the System Clock rate. If RxC and TxC are synchronized to the falling edge of the System

Clock, the maximum clock rate into RxC and TxC can be one-fourth the System Clock rate.

10. System Clock.

11. Due to the dynamic nature of the internal data bus, if CS is held low for more than a few hundred milli seconds the

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