MK68564 datasheet(16/46 Pages) STMICROELECTRONICS

16 / 46 page

Command 2 has been issued, and another Exter-

nal/Status interrupt request will be generated. This

interrupt should also be handled by issuing

Command 2 to reinitialize the external/status logic.

At the end of the break sequence, a single null char-

acter will be left in the receive data FIFO. This char-

acter should be read and discarded.

Because Parity Error and Receive Overrun Error

flags are latched, the error status that is read from

Status Register 1 reflects an error in the current

word in the receive data FIFO, plus any parity or o-

verrun errors received since the last Error Reset

command. To keep correspondence between the

state of the error FIFO and the contents of the re-

ceive data FIFO, Status Register 1 should be read

before the receive buffer. If the status is read after

the data and more than one character is stacked in

the data FIFO during the read of the receive buffer,

the status flags read will be for the next word. Keep

in mind that when a character is shifted up to the top

of the data FIFO (the receive buffer), its error flags

are shifted into Status Register 1

.An exception to the normal flow of data through the

receive data FIFO occurs when the Receive Inter-

rupt On First Character Only mode is selected. A

Special Receive Condition interrupt in this mode

holds the error data, and the character itself (even

if read from the data FIFO) until the Error Reset

command (command 6) is issued. This prevents fur-

ther data from becoming available in the receiver,

until Command 6 is issued, and allows CPU inter-

vention on the character with the error even if DMA

or block transfer techniques are being used.

SYNCHRONOUS OPERATION

INTRODUCTION

Before

describing

byte-oriented,

synchronous

transmission and reception, the three types of char-

acter synchronization - Monosync, Bysync, and Ex-

ternal Sync - require some explanation. These

modes use the x1 clock for both Transmit and Re-

ceive operations. Data is sampled on the rising edge

of the Receive Clock input (RxC). Transmitter data

transitions occur on the falling edge of the Transmit

Clock input (TxC).

The differences between Monosync, Bisync, and

External Sync are in the manner in which initial re-

ceive character synchronization is achieved. The

mode of operation must be selected before sync

characters are loaded, because the registers are u-

sed differently in the various modes. Figure 10

shows the formats for all three synchronous modes.

MONOSYNC. In the Monosync mode (8-bit sync

mode), the transmitter transmits the sync character

in Sync Word Register 1. The receiver compares the

single sync character with the programmed sync

character stored in Sync Word Register 2. A match

implies character synchronization and enables data

transfer. The SYNC pin is used as an output in this

mode and is active for the part of the receive clock

that detects the sync character.

BISYNC. In the Bisync mode (16-bit sync mode), the

transmitter transmits the sync character in Sync

Word Register 1 followed by the sync character in

Sync Word Register 2. The receiver compares the

two contiguous sync characters with the program-

med sync characters stored in Sync Word Registers

1 and 2. A match implies character synchronization

and enables data transfer. The SYNC pin is used as

an output in this mode and is active for the part of

the receive clock that detects the sync characters.

External Sync. In the External Sync mode, the

transmitter transmits the sync character in Sync

Word Register 1. Character synchronization for the

receiver is established externally. The SYNC pin is

an input that indicates that external character syn-

chronization has been achieved. After the sync pat-

tern is detected, the external logic must wait for two

full Receive Clock cycles to activate the SYNC input

pin (see figure 11). The SYNC input pin must be held

Low until character synchronization is lost. Charac-

ter assembly begins on the rising edge of the Re-

ceive Clock that precedes the falling edge of the

SYNC input pin.

In all cases, after a reset (hardware or software), the

receiver is in the Hunt phase, during which time the

SIO looks for character synchronization. The Hunt

phase can begin only when the receiver is enabled,

and data transfer can begin only when character

synchronization has been achieved. If character

synchronization is lost, the Hunt phase can be re-en-

tered by setting the Enter Hunt Mode bit in the Re-

ceiver Control Register. In the transmit mode, the

transmitter always sends the programmed number

of sync bits (8 or 16), regardless of the bits per char-

acter programmed.

In the Monosync, Bisync, and External Sync modes,

assembly of received data continues until the SIO is

reset, or until the receiver is disabled (by command

or the DCD pin in the Rx Auto Enables mode), or un-

til the CPU sets the Enter Hunt Mode bit.

After initial synchronization has been achieved, the

operation of the Monosync, Bisync, and External

Sync modes is quite similar. Any differences are

specified in the following text.

To set up the SIO for Synchronous operations, the

following registers need to be initialized : Mode

MK68564

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