MK68564 datasheet(31/46 Pages) STMICROELECTRONICS

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D3 : Receiver CRC Enable

This bit, when set to a one in a Synchronous mode

other than SDLC, is used to initiate CRC calculation

at the beginning of the last byte transferred from the

receiver shift register to the receive data FIFO. This

operation occurs independently of the number of

bytes in the receive data FIFO. As long as this bit is

set, CRC will be calculated on all characters recei-

ved (data or sync). When a particular byte is to be

excluded from CRC calculation, this bit should be re-

set to a zero before the next byte is transferred to

the receive data FIFO. If this feature is used, care-

must be taken to ensure that eight bits per character

are selected in the reciever because of an inherent

eight-bit delay from the receiver shift register to the

CRC checker.

When this bit is set to a one in SDLC mode, the SIO

will calculate CRC on all bits between the opening

and closing flags. There is no delay from the receiver

shift register to the CRC checker in SDLC mode.

This bit is ignored in Asynchronous modes.

D2 : Address Search Mode

Setting this bit to a one in SDLC mode forces the

comparison of the first non-flag character of a frame

with the address programmed in Sync Word Regis-

ter 1 or the global address (11111111). If a match

does not occur, the frame is ignored, and the recei-

ver remains idle until the next frame is detected. No

receiver interrupts can occur in this mode, unless

there is an address match. This bit is ignored in all

modes except SDLC.

D1 : Sync Character Load Inhibit

When this bit is set to a one in any Synchronous

mode except SDLC, the SIO compares the byte in

Sync Word Register 1 with the byte about to be loa-

ded into the receiver data FIFO. If the two bytes are

equal, the load is inhibited, and no receiver interrupt

will be generated by this character. CRC calculation

is performed on all bytes, whether they are loaded

into the data FIFO or not, when the receiver CRC is

enabled. Note that the register used in the compa-

rison contains the transmit sync character in Mono-

sync and External sync modes. This bit is ignored in

SDLC mode because all flag characters are auto-

matically striped in this mode without performing

CRC calculations on them.

If this bit is set to a one in Asynchronous modes, any

character received matching the contents of Sync

Word Register 1 will not be loaded into the receive

data FIFO, and no receiver interrupt will be genera-

ted for the character.

D0 : Receiver Enable

When this bit is set to a one, receiver operation be-

gins if Rx Auto Enables mode is not selected. This

bit should be set only after all receiver parameters

are established, and the receiver is completely ini-

tialized. When this bit is zero, the receiver is disabled

; the receiver CRC checker is reset, and the receiver

is in the Hunt mode.

TRANSMITTER CONTROL REGISTER

(XMTCTL)

This register contains the control bits and parame-

ters for the transmitter logic. This register is reset to

”00H” by a channel or hardware reset.

D7, D6 Transmit Bits/Character 1 and 0

The state of these two bits determine the number of

bits in each byte transferred from the transmit buffer

to the transmit shift register. All data written to the

transmit buffer must be right-justified with the least-

significant bits first. The Five Or Less mode allows

transmission of one to five bits per character ; how-

ever, the CPU should format the data characters as

shown. If Parity is enabled, one additional bit per

character will be transmitted.

BITS

CHAR 1

BITS

CHAR 0

AUTO

ENABLES

SEND

BREAK

CRC

ENABLE

DTR

RTS

ENABLE

TX BITS /

CHAR 1

TX BITS /

CHAR 0

Bits/character

(no parity)

Five or Less

D7 D 6 D 5 D4 D3 D2 D1 D0

Five or Less

Sends One Data Bit

Sends Two Data

Bits

Sends Three Data

Bits

Sends Four Data

Bits

Sends Five Data

Bits

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