AD7490

Data Sheet

Rev. E | Page 4 of 28

Parameter

Test Conditions/Comments

AD7490B

AD7490W

Unit

Min

Typ

Max

Min

Typ

Max

LOGIC INPUTS

Input High Voltage, VINH

0.7 ×

VDRIVE

0.7 ×

VDRIVE

V

Input Low Voltage, VINL

0.3 ×

VDRIVE

0.3 ×

VDRIVE

V

Input Current, IIN

VIN = 0 V or VDRIVE

±0.01

±1

±0.01

±1

µA

Input Capacitance, CIN+3

10

10

pF

LOGIC OUTPUTS

Output High Voltage, VOH

ISOURCE = 200 µA; VDD = 2.7 V to

5.25 V

VDRIVE −

0.2

VDRIVE −

0.2

V

Output Low Voltage, VOL

ISINK = 200 µA

0.4

0.4

V

Floating State Leakage Current

WEAK/TRI bit set to 0

±10

±10

µA

Floating State Output Capacitance3

WEAK/TRI bit set to 0

10

10

pF

Output Coding

Coding bit set to 1

Straight (natural) binary

Straight (natural) binary

Coding bit set to 0

Twos complement

Twos complement

CONVERSION RATE

Conversion Time

16 SCLK cycles, SCLK = 20 MHz

800

800

ns

Track-and-Hold Acquisition Time2

Sine wave input

300

300

ns

Full-scale step input

300

300

ns

Throughput Rate

VDD = 5 V (see the Serial

Interface section)

1

1

MSPS

POWER REQUIREMENTS

VDD

2.7

5.25

2.7

5.25

V

VDRIVE

2.7

5.25

2.7

5.25

V

IDD4

Digital inputs = 0 V or VDRIVE

Normal Mode (Static)

VDD = 2.7 V to 5.25 V, SCLK on or

off

600

600

µA

Normal Mode (Operational)

VDD = 4.75 V to 5.25 V,

fSCLK = 20 MHz

2.5

2.5

mA

Normal Mode (fS = Maximum

Throughput)

VDD = 2.7 V to 3.6 V,

fSCLK = 20 MHz

1.8

1.8

mA

Auto Standby Mode

fSAMPLE = 500 kSPS

1.55

1.55

mA

Static

100

100

µA

Auto Shutdown Mode

fSAMPLE = 250 kSPS

960

960

µA

Static

0.5

0.5

µA

Full Shutdown Mode

SCLK on or off

0.02

0.5

0.02

0.5

µA

Power Dissipation4

Normal Mode (Operational)

VDD = 5 V, fSCLK = 20 MHz

12.5

12.5

mW

VDD = 3 V, fSCLK = 20 MHz

5.4

5.4

mW

Auto Standby Mode (Static)

VDD = 5 V

460

480

µW

VDD = 3 V

276

276

µW

Auto Shutdown Mode (Static)

VDD = 5 V

2.5

2.5

µW

VDD = 3 V

1.5

1.5

µW

Full Shutdown Mode

VDD = 5 V

2.5

2.5

µW

VDD = 3 V

1.5

1.5

µW

1

Specifications apply for fSCLK up to 20 MHz. However, for serial interfacing requirements, see the Timing Specifications section.

2

See the Terminology section.

3

Guaranteed by characterization.

4

See the Power vs. Throughput Rate section.