ADN4621 datasheet(22/28 Pages) AD

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Data Sheet

ADN4620/ADN4621

THEORY OF OPERATION

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Rev. A | 22 of 28

The ADN4620/ADN4621 are high speed, differential signal isolators

capable of switching up to 2.5 Gbps with signal levels compliant

to TIA/EIA-644-A. The devices couple differential signals applied to

the LVDS receiver inputs across the isolation barrier to the outputs

on the other side and retransmit the bit stream or clock as LVDS.

This integration allows drop-in isolation of LVDS signal chains and

isolation of other signals, such as CML.

The LVDS receiver detects the differential voltage present across a

termination resistor on an LVDS input. An integrated digital isolator

transmits the input state across the isolation barrier, and an LVDS

driver outputs the same state as the input.

When there is a positive differential voltage of ≥100 mV across

a termination resistor between any DINx+ pin and a corresponding

DINx− pin, the corresponding DOUTx+ pin sources current. This cur-

rent flows across the connected transmission line and termination

at the receiver at the far end of the bus, while the DOUTx− pin sinks

the return current. When there is a negative differential voltage of

≤−100 mV across any DINx± pin, the corresponding DOUTx+ pin sinks

current while the DOUTx− pin sources the current. Table 22 shows

these input and output combinations.

The output drive current is between ±2.5 mA and ±4.5 mA (typically

±3.1 mA), developing between ±250 mV and ±450 mV across a

100 Ω termination resistor (RT). The received voltage is centered

around 1.2 V. Because the differential voltage (VID) reverses polari-

ty, the peak-to-peak voltage swing across RT is twice the differential

voltage magnitude (|VID|).

ISOLATION AND REFRESH

In response to any change in the input state detected by the

integrated LVDS receiver, an encoder circuit sends narrow (~1 ns)

pulses to a decoder circuit using integrated transformer coils. The

decoder is bistable and is, therefore, either set or reset by the

pulses that indicate input transitions. The decoder state determines

the LVDS driver output state in normal operation, which reflects the

isolated LVDS buffer input state.

For normal operation of the ADN4620/ADN4621, the active low

enable pins on the SSOP models, REFRESH1 and REFRESH2,

are shorted to the same respective PCB grounds as the GND1

and GND2 pins to enable a refresh function. When enabled, this

function means that in the absence of input transitions for more

than approximately 1 µs, a periodic set of refresh pulses, indicative

of the correct input state, ensures dc correctness at the output

(including the fail-safe output state, if applicable). This function is

permanently enabled for the SOIC_IC models.

On power-up, the output state may initially be in the incorrect dc

state if there are no input transitions. The output state is corrected

within 1 µs by the refresh pulses.

If the decoder receives no internal pulses for more than approxi-

mately 1 µs, the device assumes that the input side is unpowered

or nonfunctional, in which case the output is set to a positive

differential voltage (logic high).

For clocks, constant bit streams, or protocols with error correction,

the refresh functionality may not be required. If the REFRESH1

and REFRESH2 pins on the SSOP models are shorted to the

same respective power supplies as the VDD1 and VDD2 pins, the

refresh functionality is disabled, allowing for lower power operation

with no internal clock-like signals (potentially reducing conducted or

radiated emissions). In this mode of operation, a new data transition

at the input may be required to correct the output state, either

after power-up or after a common-mode transient event beyond the

guaranteed common-mode transient immunity specification.

TRUTH TABLE

The LVDS standard, TIA/EIA-644-A, defines normal receiver opera-

tion under two conditions: an input differential voltage of ≥+100 mV

corresponding to one logic state, and a voltage of ≤−100 mV for

the other logic state. Between these thresholds, the standard LVDS

receiver operation is undefined (the LVDS receiver can detect either

state), as shown in Table 22.

Table 22. Input and Output Operation

Input (DINx±)

Output (DOUTx±)

Powered On

VID (mV)

Logic

Powered On

VOD (mV)

Logic

Yes

≥100

High

Yes

≥250

High

Yes

≤−100

Low

Yes

≤−250

Low

Yes

−100 < VID < +100

Indeterminate

Yes

Indeterminate

Don’t care

Yes

≥250

High

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