AD7699

Data Sheet

Rev. F | Page 6 of 32

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VREF = 4.096 to VDD, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

tCONV

LFCSP

1.6

µs

WLCSP

1.675

µs

Acquisition Time

tACQ

LFCSP

400

ns

WLCSP

325

ns

Time Between Conversions2

tCYC

2

µs

CNV Pulse Width

tCNVH

10

ns

Data Write/Read During Conversion

tDATA

1.2

µs

SCK Period

tSCK

tDSDO + 2

ns

SCK Low Time

tSCKL

11

ns

SCK High Time

tSCKH

11

ns

SCK Falling Edge to Data Remains Valid

tHSDO

4

ns

SCK Falling Edge to Data Valid Delay

tDSDO

VIO Above 4.5 V

16

ns

VIO Above 3 V

17

ns

VIO Above 2.7 V

18

ns

VIO Above 2.3 V

21

ns

VIO Above 1.8 V

28

ns

CNV Low to SDO D15 MSB Valid

tEN

VIO Above 4.5 V

15

ns

VIO Above 3 V

17

ns

VIO Above 2.7 V

18

ns

VIO Above 2.3 V

22

ns

VIO Above 1.8 V

25

ns

CNV High or Last SCK Falling Edge to SDO High Impedance

tDIS

32

ns

CNV Low to SCK Rising Edge

tCLSCK

10

ns

Last SCK Falling Edge to CNV Rising Edge Delay

tQUIET

40

ns

DIN Valid Setup Time from SCK Rising Edge

tSDIN

5

ns

DIN Valid Hold Time from SCK Rising Edge

tHDIN

5

ns

1

See Figure 2 and Figure 3 for load conditions.

2

For the WLCSP, a full throughput of 500kSPS can only be achieved using read during conversion or read spanning conversion mode.

IOL

500µA

500µA

IOH

1.4V

TO SDO

CL

50pF

Figure 2. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

2V OR VIO – 0.5V1

0.8V OR 0.5V2

0.8V OR 0.5V2

2V OR VIO – 0.5V1

tDELAY

tDELAY

1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing