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DSP56301 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc |
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DSP56301 Datasheet(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 124 page  AC Electrical Characteristics DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-13 2.5.5.1 SRAM Timing Table 2-8. SRAM Read and Write Accesses3,6 No. Characteristics Symbol Expression1 80 MHz 100 MHz Unit Min Max Min Max 100 Address valid and AA assertion pulse width2 tRC, tWC (WS + 1) × TC − 4.0 [1 ≤ WS ≤ 3] (WS + 2) × TC − 4.0 [4 ≤ WS ≤ 7] (WS + 3) × TC − 4.0 [WS ≥ 8] 21.0 71.0 133.5 — — — 16.0 56.0 106.0 — — — ns ns ns 101 Address and AA valid to WR assertion tAS 0.25 × TC − 2.0 [WS = 1] 0.75 × TC − 2.0 [2 ≤ WS ≤ 3] 1.25 × TC − 2.0 [WS ≥ 4] 1.1 7.4 13.6 — — — 0.5 5.5 10.5 — — — ns ns ns 102 WR assertion pulse width tWP 1.5 × TC − 4.0 [WS = 1] WS × TC − 4.0 [2 ≤ WS ≤ 3] (WS − 0.5) × TC − 4.0 [WS ≥ 4] 14.8 21.0 39.8 — — — 11.0 16.0 31.0 — — — ns ns ns 103 WR deassertion to address not valid tWR 0.25 × TC − 2.0 [1 ≤ WS ≤ 3] 1.25 × TC − 4.0 [4 ≤ WS ≤ 7] 2.25 × TC − 4.0 [WS ≥ 8] 1.1 11.6 24.1 — — — 0.5 8.5 18.5 — — — ns ns ns 104 Address and AA valid to input data valid tAA, tAC (WS + 0.75) × TC − 5.0 [WS ≥ 1] — 16.9 — 12.5 ns 105 RD assertion to input data valid tOE (WS + 0.25) × TC − 5.0 [WS ≥ 1] — 10.6 — 7.5 ns 106 RD deassertion to data not valid (data hold time) tOHZ 0.0 — 0.0 — ns 107 Address valid to WR deassertion2 tAW (WS + 0.75) × TC − 4.0 [WS ≥ 1] 17.9 — 13.5 — ns 108 Data valid to WR deassertion (data setup time) tDS (tDW)(WS − 0.25) × TC − 3.0 [WS ≥ 1] 6.4 — 4.5 — ns 109 Data hold time from WR deassertion tDH 0.25 × TC − 2.0 [1 ≤ WS ≤ 3] 1.25 × TC − 2.0 [4 ≤ WS ≤ 7] 2.25 × TC − 2.0 [WS ≥ 8] 1.1 13.6 26.1 — — — 0.5 10.5 20.5 — — — ns ns ns 110 WR assertion to data active 0.75 × TC − 3.7 [WS = 1] 0.25 × TC − 3.7 [2 ≤ WS ≤ 3] −0.25 × TC − 3.7 [WS ≥ 4] 5.7 –0.6 –6.8 — — — 3.8 –1.2 –6.2 — — — ns ns ns 111 WR deassertion to data high impedance 0.25 × TC + 0.2 [1 ≤ WS ≤ 3] 1.25 × TC + 0.2 [4 ≤ WS ≤ 7] 2.25 × TC + 0.2 [WS ≥ 8] — — — 3.3 15.8 28.3 — — — 2.7 12.7 22.7 ns ns ns 112 Previous RD deassertion to data active (write) 1.25 × TC − 4.0 [1 ≤ WS ≤ 3] 2.25 × TC − 4.0 [4 ≤ WS ≤ 7] 3.25 × TC − 4.0 [WS ≥ 8] 11.6 24.1 36.6 — — — 8.5 18.5 28.5 — — — ns ns ns 113 RD deassertion time 0.75 × TC − 4.0 [1 ≤ WS ≤ 3] 1.75 × TC − 4.0 [4 ≤ WS ≤ 7] 2.75 × TC − 4.0 [WS ≥ 8] 5.4 17.9 30.4 — — — 3.5 13.5 23.5 — — — ns ns ns 114 WR deassertion time 0.5 × TC − 4.0 [WS = 1] TC − 4.0 [2 ≤ WS ≤ 3] 2.5 × TC − 4.0 [4 ≤ WS ≤ 7] 3.5 × TC − 4.0 [WS ≥ 8] 2.3 8.5 27.3 39.8 — — — — 1.0 6.0 21.0 31.0 — — — — ns ns ns ns |
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