DSP56301 datasheet(2/124 Pages) FREESCALE

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DSP56301 Technical Data, Rev. 10

Freescale Semiconductor

Table of Contents

DSP56301 Features.............................................................................................................................................iii

Target Applications .............................................................................................................................................iv

Product Documentation ......................................................................................................................................iv

Chapter 1

Signals/Connections

1.1

Power ................................................................................................................................................................1-4

1.2

Ground ..............................................................................................................................................................1-4

1.3

Clock.................................................................................................................................................................1-5

1.4

Phase Lock Loop (PLL)....................................................................................................................................1-5

1.5

External Memory Expansion Port (Port A) ......................................................................................................1-6

1.6

Interrupt and Mode Control ..............................................................................................................................1-9

1.7

Host Interface (HI32)......................................................................................................................................1-10

1.8

Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-16

1.9

Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-18

1.10

Serial Communication Interface (SCI) ...........................................................................................................1-19

1.11

Timers .............................................................................................................................................................1-20

1.12

JTAG/OnCE Interface.....................................................................................................................................1-21

Chapter 2

Specifications

2.1

Maximum Ratings.............................................................................................................................................2-1

2.2

Absolute Maximum Ratings .............................................................................................................................2-2

2.3

Thermal Characteristics ....................................................................................................................................2-2

2.4

DC Electrical Characteristics............................................................................................................................2-2

2.5

AC Electrical Characteristics............................................................................................................................2-4

Chapter 3

Packaging

3.1

TQFP Package Description...............................................................................................................................3-2

3.2

TQFP Package Mechanical Drawing..............................................................................................................3-11

3.3

MAP-BGA Package Description ....................................................................................................................3-12

3.4

MAP-BGA Package Mechanical Drawing .....................................................................................................3-23

Chapter 4

Design Considerations

4.1

Thermal Design Considerations........................................................................................................................4-1

4.2

Electrical Design Considerations......................................................................................................................4-2

4.3

Power Consumption Considerations.................................................................................................................4-3

4.4

PLL Performance Issues ...................................................................................................................................4-4

4.5

Input (EXTAL) Jitter Requirements .................................................................................................................4-4

Chapter A

Power Consumption Benchmark

Index

Data Sheet Conventions

OVERBAR

Indicates a signal that is active when pulled low (For example, the RESET pin is active when

low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted”

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

True

Asserted

VIL/VOL

False

Deasserted

VIH/VOH

True

Asserted

VIH/VOH

False

Deasserted

VIL/VOL

Note:

Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

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