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DSP56301 Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc |
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DSP56301 Datasheet(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 124 page  AC Electrical Characteristics DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-23 Table 2-13. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 No. Characteristics3 Symbol Expression 80 MHz 100 MHz Unit Min Max Min Max 157 Random read or write cycle time tRC 12 × TC 150.0 — 120.0 — ns 158 RAS assertion to data valid (read) tRAC 80 MHz: 6.25 × TC − 6.5 100 MHz: 6.25 × TC − 7.0 — — 71.6 — — — — 55.5 ns ns 159 CAS assertion to data valid (read) tCAC 80 MHz: 3.75 × TC − 6.5 100 MHz: 3.75 × TC − 7.0 — — 40.4 — — — — 30.5 ns ns 160 Column address valid to data valid (read) tAA 80 MHz: 4.5 × TC − 6.5 100 MHz: 4.5 × TC − 7.0 — — 49.8 — — — — 38.0 ns ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 — 0.0 — ns 162 RAS deassertion to RAS assertion tRP 4.25 × TC − 4.0 49.1 — 38.5 — ns 163 RAS assertion pulse width tRAS 7.75 × TC − 4.0 92.9 — 73.5 — ns 164 CAS assertion to RAS deassertion tRSH 5.25 × TC − 4.0 61.6 — 48.5 — ns 165 RAS assertion to CAS deassertion tCSH 6.25 × TC − 4.0 74.1 — 58.5 — ns 166 CAS assertion pulse width tCAS 3.75 × TC − 4.0 42.9 — 33.5 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × TC ± 4.0 27.3 35.3 21.0 29.0 ns 168 RAS assertion to column address valid tRAD 1.75 × TC ± 4.0 17.9 25.9 13.5 21.5 ns 169 CAS deassertion to RAS assertion tCRP 5.75 × TC − 4.0 67.9 — 53.5 — ns 170 CAS deassertion pulse width tCP 4.25 × TC – 6.0 49.1 — 36.5 — ns 171 Row address valid to RAS assertion tASR 4.25 × TC − 4.0 49.1 — 38.5 — ns 172 RAS assertion to row address not valid tRAH 1.75 × TC − 4.0 17.9 — 13.5 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 5.4 — 3.5 — ns 174 CAS assertion to column address not valid tCAH 5.25 × TC − 4.0 61.6 — 48.5 — ns 175 RAS assertion to column address not valid tAR 7.75 × TC − 4.0 92.9 — 73.5 — ns 176 Column address valid to RAS deassertion tRAL 6 × TC − 4.0 71.0 — 56.0 — ns 177 WR deassertion to CAS assertion tRCS 3.0 × TC − 4.0 33.5 — 26.0 — ns 178 CAS deassertion to WR4 assertion tRCH 1.75 × TC – 3.7 17.9 — 13.8 — ns 179 RAS deassertion to WR4 assertion tRRH 80 MHz: 0.25 × TC − 2.6 100 MHz: 0.25 × TC − 2.0 0.5 — — — — 0.5 — — ns ns 180 CAS assertion to WR deassertion tWCH 5 × TC − 4.2 58.3 — 45.8 — ns 181 RAS assertion to WR deassertion tWCR 7.5 × TC − 4.2 89.6 — 70.8 — ns 182 WR assertion pulse width tWP 11.5 × TC − 4.5 139.3 — 110.5 — ns 183 WR assertion to RAS deassertion tRWL 11.75 × TC − 4.3 142.7 — 113.2 — ns 184 WR assertion to CAS deassertion tCWL 10.25 × TC − 4.3 123.8 — 98.2 — ns 185 Data valid to CAS assertion (write) tDS 5.75 × TC − 4.0 67.9 — 53.5 — ns 186 CAS assertion to data not valid (write) tDH 5.25 × TC − 4.0 61.6 — 48.5 — ns |
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