LTC4252-2CMSTR datasheet(24/36 Pages) LINER

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LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

425212fb

APPLICATIO S I FOR ATIO

Undervoltage Timing

In Figure 11 when UV pin drops below VUVLO(time point 1),

the LTC4252 shuts down with TIMER, SS and GATE all

pulling low. If current has been flowing, the SENSE pin

voltage decreases to zero as GATE collapses. When UV

recovers and clears VUVHI (time point 2), an initial timer

cycle begins followed by a GATE start-up cycle.

VIN Undervoltage Lockout Timing

The VIN undervoltage lockout comparator, UVLO, has a

similar timing behavior as the UV pin timing except it looks

for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to

start. In an undervoltage lockout condition, both UV and

OV comparators are held off. When VIN exits undervoltage

lockout, the UV and OV comparators are enabled.

Undervoltage Timing with Overvoltage Glitch

In Figure 12, both UV and OV pins are connected together.

When UV clears VUVHI (time point 1), an initial timing cycle

starts. If the system bus voltage overshoots VOVHI as

shown at time point 2, TIMER discharges. At time point 3,

the supply voltage recovers and drops below the VOVLO

threshold. The initial timing cycle restarts, followed by a

GATE start-up cycle.

Overvoltage Timing

During normal operation, if the OV pin exceeds VOVHI as

shown at time point 1 of Figure 13, the TIMER and PWRGD

status are unaffected. Nevertheless, SS and GATE pull

down and the load is disconnected. At time point 2, OV

recovers and drops below the VOVLO threshold. A GATE

start-up cycle begins. If the overvoltage glitch is long

enough to deplete the load capacitor, a full start-up cycle

as shown between time points 4 through 7 may occur.

Circuit Breaker Timing

In Figure 14a, the TIMER capacitor charges at 230

µA if the

SENSE pin exceeds VCB but VDRN is less than 5V. If the

SENSE pin drops below VCB before TIMER reaches the

Figure 11. Undervoltage Timing (All Waveforms are Referenced to VEE)

TIMER

GATE

SENSE

DRAIN

PWRGD

5.8

µA

5.8

µA

5.8

µA

UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES

3 4 56

8 9

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

10 11

4252-1/2 F11

UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

VACL

VCB

230

µA + 8 • IDRN

20 • VOS

VIN – VGATEH

VDRNL

VDRNCL

20 • (VCB + VOS)

20 • (VACL + VOS)

VGATEL

VTMRL

VTMRH

VUVHI

VUVLO

GATE

START-UP

INITIAL TIMING

LTC4252-2CMSTR Datasheet(PDF) 24 Page - Linear Technology

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