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LTC4252-2CMSTR Datasheet(PDF) 26 Page - Linear Technology |
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LTC4252-2CMSTR Datasheet(HTML) 26 Page - Linear Technology |
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26 / 36 page ![]() LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 26 425212fb APPLICATIO S I FOR ATIO VTMRH threshold, TIMER is discharged by 5.8µA. In Figure 14b, when TIMER exceeds VTMRH, GATE pulls down immediately and the LTC4252 shuts down. In Figure 14c, multiple momentary faults cause the TIMER capacitor to integrate and reach VTMRH. GATE pull down follows and the LTC4252 shuts down. During shutdown, the LTC4252-1 latches TIMER high with a 5.8 µA pull-up current source; the LTC4252-2 activates a shutdown cooling cycle. Resetting a Fault Latch (LTC4252-1) The latched circuit breaker fault of LTC4252-1 benefits from long cooling time. It is reset by pulling the UV pin below VUVLO with a switch. Reset is also accomplished by pulling the VIN pin momentarily below (VLKO – VLKH). A third reset method involves pulling the TIMER pin below VTMRL as shown in Figure 15. An initial timing cycle is skipped if TIMER is used for reset. An initial timing cycle is generated if reset by the UV pin or the VIN pin. The duration of the TIMER reset pulse should be smaller than the time taken to reach 0.2V at SS pin. With a single pole mechanical pushbutton switch, this may not be feasible. A double pole, single throw pushbutton switch removes this restriction by connecting the second switch to the SS pin. With this method, both the SS and TIMER pins are released at the same time (see Figure 24). Shutdown Cooling Cycle (LTC4252-2) Figure 16 shows the timer behavior of the LTC4252-2. At time point 2, TIMER exceeds VTMRH, GATE pulls down immediately and the LTC4252 shuts down. TIMER starts a shutdown cooling cycle by discharging TIMER with 5.8 µA to the VTMRL threshold. TIMER then charges with 5.8 µA to the VTMRH threshold. There are four 5.8µA discharge phases and three 5.8 µA charge phases in this shutdown cooling cycle spanning time points 2 and 3. At time point 3, the LTC4252 automatic retry occurs with a start-up cycle. Good thermal management techniques are highly recommended; power and thermal dissipation must be carefully evaluated when implementing the automatic retry scheme. (14a) Momentary Circuit-Breaker Fault Figure 14. Circuit-Breaker Timing Behavior (All Waveforms are Referenced to VEE) (14b) Circuit-Breaker Time Out (14c) Multiple Circuit-Breaker Fault CB FAULT TIMER GATE SENSE VOUT SS DRAIN PWRGD TIMER GATE SENSE VOUT SS DRAIN PWRGD TIMER GATE SENSE VOUT SS DRAIN PWRGD CB FAULT CB FAULT CB FAULT 5.8 µA 5.8 µA 12 4252-1/2 F14 12 CB TIMES OUT 14 3 2 CB TIMES OUT VACL VCB VACL VDRNCL VCB VACL VTMRH VTMRH VTMRH VCB 230 µA + 8 • IDRN VDRNCL 230 µA + 8 • IDRN 230 µA + 8 • IDRN 230 µA + 8 • IDRN |
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