WM8580 datasheet(42/103 Pages) WOLFSON

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WM8580

Production Data

PD Rev 4.5 February 2008

CLOCK SELECTION

To accompany the flexible digital routing options, the WM8580 offers a similar flexible clock

configuration capability. The user can chose which clock drives each of the main functional blocks. In

general the choice of clock is between MCLK, ADCMCLK, PLLACLK and PLLBCLK, with some

restrictions dependant upon the digital routing configuration. An example of the restrictions is if the

S/PDIF receiver is routed to DAC1, then the appropriate clock for DAC1 is autoconfigured. Not all 4

clocks are available to all main function blocks. For the purposes of description, Table 33 defines the

signal names and descriptions used in the following sections.

Signal Name

Description

MCLK

System Master Clock pin

ADCMCLK

ADC Masetr clock input pin (MFP2)

PLLACLK

Output of PLLA (following any programmed division)

PLLBCLK

Output of PLLB (following any programmed division)

DAC_CLK

The internal clock driving all DAC functional blocks

DAC_CLK_SEL

User programmed register select bits to select DAC_CLK (Reg8, bits 1:0)

DAC_CLK_SEL_I

Internally generated multiplexer select bits to select DAC_CLK – generated based on

DAC_CLK_SEL register bits and digital routing configuration.

ADC_CLK

The internal clock driving the ADC functional block

ADC_CLK_SEL_I

Internally generated multiplexer select bits to select ADC_CLK – generated based on

ADC_CLK_SEL register bits and digital routing configuration.

ADC_CLK_SEL

User programmed register select bits to select ADC_CLK (Reg8, bits 3:2)

TX_CLK

The internal clock driving the S/PDIF Tx functional block

TX_CLKSEL_I

Internally generated multiplexer select bits to select TX_CLK – generated based on

TX_CLKSEL register bits and digital routing configuration.

TX_CLKSEL

User programmed register select bits (Reg8, bits 5:4) to select TX_CLK

PAIFRXMS_CLKSEL

User programmed register select bits (Reg9, bits 7:6) to select PAIF Rx interface input clock

when the PAIF Rx is configured in master mode. In master mode, the PAIF Rx generates a

BCLK and an LRCLK from the selected clock source. When in Slave mode the PAIF Rx uses

the input pins PAIFRX_BCLK and PAIFRX_LRCLK

PAIFRXMS_CLKSEL_I

Internally generated multiplexer select bits to select PAIF Rx clock source – generated based

on PAIFRXMS_CLKSEL register bits and digital routing configuration.

PAIFTXMS_CLKSEL

User programmed register select bits (Reg??, bits ??) to select PAIF Tx interface input clock

when the PAIF Tx is configured in master mode. In master mode, the PAIF Tx generates a

BCLK and an LRCLK from the selected clock source. When in Slave mode the PAIF Tx uses

the input pins PAIFTX_BCLK (MFP1) and PAIFTX_LRCLK

PAIFTXMS_CLKSEL_I

Internally generated multiplexer select bits to select PAIF Rx clock source – generated based

on PAIFRXMS_CLKSEL register bits and digital routing configuration.

SAIF_CLKSEL

User programmed register select bits (Reg11, bits 7:6) to select SAIF (Tx and Rx) interface

input clock when the SAIF is configured in master mode. In master mode, the SAIF

generates a BCLK and an LRCLK from the selected clock source. When in Slave mode the

SAIF uses the input pins SAIF_BCLK (MFP6) and SAIF_LRCLK (MFP7).

SAIF_CLKSEL_I

Internally generated multiplexer select bits to select SAIF clock source – generated based on

SAIF_CLKSEL register bits and digital routing configuration.

Table 33 Definition of Signal Names for Purpose of Description

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