WM8580 datasheet(65/103 Pages) WOLFSON

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WM8580

PD Rev 4.5 February 2008

Table 61 S/PDIF Receiver Input Selection Register

AUDIO DATA HANDLING

The S/PDIF receiver recovers the data and VUCP bits from each sub-frame. If the S/PDIF input data

is in a non-compressed audio format the data can be internally routed to the stereo data input of

DAC1. The WM8580 can detect when the data is in a non-compressed audio format and will

automatically mute the DAC. See Non-Audio Detection section for more detail.

The received data can also be output over the digital audio interfaces in any of the data formats

supported. This can be performed while simultaneously using DAC1 for playback. The received data

may also be re-transmitted via the S/PDIF transmitter.

USER DATA

The WM8580 can output recovered user data received using GPO pins. See Table 72 for General

Purpose Pin control information.

CHANNEL STATUS DATA

The channel status bits are recovered from the incoming data stream and are used to control various

functions of the device.

The S/PDIFRx interface always receives 24 bits of data in bits 4 to 27 of the SPDIF payload. The

audio sample can be either 20 bits if AUX bits not used or up to 24bits if AUX bits used (refer to

Figure 39). So the audio sample can be 20,21,22,23 or 24 bit. The source (wherever the S/PDIF data

is coming from) of the S/PDIF data stream must set the MAXWL and RXWL within the status bits to

indicate the size of the audio sample. This is then recovered by the S/PDIF Rx interface. The S/PDIF

Rx interface ALWAYS receives 24 bits, but if the actual length of the audio data sample (indicated by

MAXWL and RXWL) is less than 24 bits, then the user has the option to truncate these 24 bits to the

actual size. These truncated bits are then sent to either the SPDIF Tx or the AIF. Truncation may

allow users to process data faster. If the user does not want this truncation to happen then they must

mask the truncation using the WL_MASK. In this case all 24 bits of data received are transferred.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

SPDIFIN1MODE

Selects the input circuit type for the SPDIFIN1 input

0 = CMOS-compatible input

1 = Comparator input. Compatible with 500mVpp AC

coupled consumer S/PDIF input signals as defined in

IEC60958-3.

2:1

RXINSEL[1:0]

S/PDIF Receiver input mux select.

The general purpose inputs must be configured using

GPOxOP to be either CMOS or comparator inputs if

selected by RXINSEL.

00 = Select SPDIFIN1

01 = Select SPDIFIN2 (MFP3)

10 = Select SPDIFIN3 (MFP4)

11 = Select SPDIFIN4 (MFP5)

R36

SPDMODE

24h

WL_MASK

S/PDIF Receiver Word Length Truncation Mask

0 = disabled, data word is truncated as described in

Table 66.

1 = enabled, data word is not truncated.

3:0

GPO3OP[3:0]

0010

R39

GPO2

27h

7:4

GPO4OP[3:0]

0011

R40

GPO3

28h

3:0

GPO5OP[3:0]

0100

GPO pin Configuration Select.

1110 = Set GPO as S/PDIF input (CMOS-compatible

input).

1111 = Set GPO as S/PDIF input (compatible with

500mVpp AC coupled consumer S/PDIF input signals

as defined in IEC-60958-3).

For GPO defaults, see Table 72.

R51

PWRDN 2

33h

SPDIFRXD

S/PDIF Receiver powerdown.

0 = S/PDIF Receiver enabled

1 = S/PDIF Receiver disabled

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