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WM8580 Datasheet(PDF) 82 Page - Wolfson Microelectronics plc |
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WM8580 Datasheet(HTML) 82 Page - Wolfson Microelectronics plc |
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82 / 103 page  WM8580 Production Data w PD Rev 4.5 February 2008 82 REGISTER NAME ADDRESS B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT R39 GPO2 27 ALWAYSVALID GPO4OP[3:0] GPO30P[3:0] 000110010 R40 GPO3 28 0 GPO6OP[3:0] GPO5OP[3:0] 001010100 R41 GPO4 29 0 GPO8OP[3:0] GPO70P[3:0] 001110110 R42 GPO5 2A 0 GPO10OP[3:0] GPO9OP[3:0] 010011000 R43 INTSTAT 2B Error Flag Interupt Status Register Read-only R44 SPDRXCHAN 1 2C Channel Status Register 1 Read-only R45 SPDRXCHAN 2 2D Channel Status Register 2 Read-only R46 SPDRXCHAN 3 2E Channel Status Register 3 Read-only R47 SPDRXCHAN 4 2F Channel Status Register 4 Read-only R48 SPDRXCHAN 5 30 Channel Status Register 5 Read-only R49 SPDSTAT 31 S/PDIF Status Register Read-only R50 PWRDN 1 32 0 0 ALLDACPD 1 DACPD[2:0] ADCPD PWDN 001111110 R51 PWRDN 2 33 0 0 0 SPDIFRXD SPDIFTXD SPDIFPD PLLBPD PLLAPD OSCPD 000111110 R52 READBACK 34 0 0 0 0 READEN CONTREAD READMUX[2:0] 000000000 R53 RESET 35 RESET n/a REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 PLLA 1/ DEVID1 00h 8:0 PLLA_K[8:0] 100100001 R1 PLLA 2/ DEVID2 01h 8:0 PLLA_K[17:9] 101111110 3:0 PLLA_K[21:18] 1101 Fractional (K) part of PLLA frequency rIio (R). Value K is one 22-digit binary number spread over registers R0, R1 and R2 as shown. Reading from these registers will return the device ID. R0 returns 10000000 = 80h R1 returns 10000101 = 85h Device ID readback is not possible in continuous readback mode (CONTREAD=1). R2 PLLA 3/ DEVREV 02h 7:4 PLLA_N[3:0] 0111 Integer (N) part of PLLA frequenIratio (R). Use values in the range 5 ≤ PLLA_N ≤ 13 as close as possible to 8. Reading from this register will return the device revision number. 0 PRESCALE_A 0 PLL Pre-scale Divider Select 0 = Divide by 1 (PLL input clock = oscillator clock) 1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2) Note: PRESCALE_A must be set to the same value as PRESCALE_B in PLL S/PDIF receiver mode. 1 POSTSCALE_A 0 PLL Post-scale Divider Select PLL S/PDIF Receiver Mode POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK, POSTSCALE_B is not used. Refer to Table 51. PLL User Mode Used in conjunction with the FREQMODE_x bits. Refer to Table 50. R3 PLLA 4 03h 4:3 FREQMODE_A[ 1:0] 10 PLL Output Divider Select PLL S/PDIF Receiver Mode FREQMODE_A is automatically controlled. FREQMODE_B is not used. PLL User Mode Used in conjunction with the POSTSCALE_x bits. Refer to Table 50. |
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