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ST72325 Datasheet(PDF) 92 Page - STMicroelectronics |
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ST72325 Datasheet(HTML) 92 Page - STMicroelectronics |
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92 / 196 page  92/196 10.5 SERIAL PERIPHERAL INTERFACE (SPI) 10.5.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system. 10.5.2 Main Features ■ Full duplex synchronous transfers (on 3 lines) ■ Simplex synchronous transfers (on 2 lines) ■ Master or slave operation ■ Six master mode frequencies (fCPU/4 max.) ■ fCPU/2 max. slave mode frequency (see note) ■ SS Management by software or hardware ■ Programmable clock polarity and phase ■ End of transfer interrupt flag ■ Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 10.5.3 General Description Figure 56 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: – SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR) The SPI is connected to external devices through 4 pins: – MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI masters and in- put by SPI slaves Figure 56. Serial Peripheral Interface Block Diagram SPIDR Read Buffer 8-Bit Shift Register Write Read Data/Address Bus SPI SPIE SPE MSTR CPHA SPR0 SPR1 CPOL SERIAL CLOCK GENERATOR MOSI MISO SS SCK CONTROL STATE SPICR SPICSR Interrupt request MASTER CONTROL SPR2 0 7 0 7 SPIF WCOL MODF 0 OVR SSI SSM SOD SOD bit SS 1 0 |
Similar Part No. - ST72325_07 |
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Similar Description - ST72325_07 |
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