ST72325_07 datasheet(33/196 Pages) STMICROELECTRONICS

Part #	ST72325

Description	8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2.2 Monitoring a Voltage on the EVD pin

This mode is selected by setting the AVDS bit in

the SICSR register.

The AVD circuitry can generate an interrupt when

the AVDIE bit of the SICSR register is set. This in-

terrupt is generated on the rising and falling edges

of the comparator output. This means it is generat-

ed when either one of these two events occur:

–VEVD rises up to VIT+(EVD)

–VEVD falls down to VIT-(EVD)

The EVD function is illustrated in Figure 19.

For more details, refer to the Electrical Character-

istics section.

Figure 19. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)

VEVD

VIT+(EVD)

VIT-(EVD)

AVDF

0

1

IF AVDIE = 1

Vhyst

AVD INTERRUPT

REQUEST

INTERRUPT PROCESS

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