Z Address Counter
The Z address counter generates addresses for outputting the display data synchronized with the
common signal. This counter consists of 6 bits and counts up at the fall of the CL signal. At the high
level of FRM, the contents of the display start line register is preset at the Z counter.
Display Data Latch
The display data latch stores the display data temporarily that is output from display data RAM to the
liquid crystal driving circuit. Data is latched at the rise of the CL signal. The display on/off instruction
controls the data in this latch and does not influence data in display data RAM.
Liquid Crystal Display Driver Circuit
The combination of latched display data and M signal causes one of the 4 liquid crystal driver levels,
V1, V2, V3 and V4 to be output.
Reset
The system can be initialized by setting RST terminal at low level when turning power on.
1. Display off
2. Set display start line register line 0.
While RST is low level, no instruction except status read can be accepted. Therefore, execute other
instructions after making sure that DB4 = 0 (clear RESET) and DB7 = 0 (Ready) by status read
instruction. The conditions of power supply at initial power up are shown in table 1.
Do not fail to set the system again becaise RESET during operation may destroy the data in
all the registers except on/off register and in RAM.
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AX6108 Dot Matrix Liquid Crystal Graphic Display Column Driver
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ASLIC MICROELECTRONICS CORP.
Page 20
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Table 1 Power Supply Initial Conditions
Item
Symbol
Min
Typ
Max
Unit
Reset time
Rise time
t
RST
tr
1.0
200
£gs
ns
4.5V
t
tr
RST
0.7Vcc
0.3Vcc
RST
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