TMS320DM335 datasheet(120/156 Pages) TI

120 / 156 page

5.9.1.4 VPFE Electrical Data/Timing

PCLK

TMS320DM335

Digital Media System-on-Chip (DMSoC)

SPRS528 – JULY 2008

www.ti.com

Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode(1) (see Figure 5-23)

NO.

MIN

MAX

UNIT

H3A not used

13.33 or P(2)

100

tc(PCLK)

Cycle time, PCLK

H3A used

2P + 1

100

tw(PCLKH)

Pulse duration, PCLK high

5.7

tw(PCLKL)

Pulse duration, PCLK low

5.7

tt(PCLK)

Transition time, PCLK

(1)

P = 1/SYSCLK4 in nanoseconds (ns). For example, if the SYSCLK4 frequency is 135 MHz, use P = 7.41 ns. See Section 3.5, Device

Clocking, for more information on the supported clock configurations of the DM335.

(2)

Use whichever value is greater.

Figure 5-23. VPFE PCLK Timing

Table 5-18. Timing Requirements for VPFE (CCD) Slave Mode (see Figure 5-24)

DM335

NO.

UNIT

MIN

MAX

tsu(CCDV-PCLK)

Setup time, CCD valid before PCLK edge

th(PCLK-CCDV)

Hold time, CCD valid after PCLK edge

tsu(HDV-PCLK)

Setup time, HD valid before PCLK edge

th(PCLK-HDV)

Hold time, HD valid after PCLK edge

tsu(VDV-PCLK)

Setup time, VD valid before PCLK edge

th(PCLK-VDV)

Hold time, VD valid after PCLK edge

tsu(CAM_WEN_FIELD

Setup time, CAM_WEN_FIELD valid before PCLK edge

V-PCLK)

th(CAM_WEN_FIELDV

Hold time, C_WEN_FIELD valid after PCLK edge

-PCLK)

DM335 Peripheral Information and Electrical Specifications

120

Submit Documentation Feedback

TMS320DM335 Datasheet(PDF) 120 Page - Texas Instruments

TMS320DM335 Datasheet(HTML) 120 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL