TMS320DM335 datasheet(124/156 Pages) TI

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5.9.2.3 VPBE Electrical Data/Timing

PCLK

EXTCLK

TMS320DM335

Digital Media System-on-Chip (DMSoC)

SPRS528 – JULY 2008

www.ti.com

• Internal Color Bar Generation (100%/75%)

• YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input

Table 5-21. Timing Requirements for VPBE CLK Inputs (see Figure 5-27)

DM335

NO.

UNIT

MIN

MAX

tc(PCLK)

Cycle time, PCLK(1)

13.33

160

tw(PCLKH)

Pulse duration, PCLK high

5.7

tw(PCLKL)

Pulse duration, PCLK low

5.7

tt(PCLK)

Transition time, PCLK

tc(EXTCLK)

Cycle time, EXTCLK

13.33

160

tw(EXTCLKH)

Pulse duration, EXTCLK high

5.7

tw(EXTCLKL)

Pulse duration, EXTCLK low

5.7

tt(EXTCLK)

Transition time, EXTCLK

(1)

For timing specifications relating to PCLK see Table 5-17, Timing Requirements for VPFE PCLK Master/Slave Mode.

Figure 5-27. VPBE PCLK and EXTCLK Timing

Table 5-22. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK(1)(2)(3) (see

Figure 5-28)

DM335

NO.

UNIT

MIN

MAX

tsu(VCTLV-VCLKIN)

Setup time, VCTL valid before VCLKIN edge

th(VCLKIN-VCTLV)

Hold time, VCTL valid after VCLKIN edge

(1)

The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the

rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.

(2)

VCTL = HSYNC, VSYNC, and FIELD

(3)

VCLKIN = PCLK or EXTCLK

DM335 Peripheral Information and Electrical Specifications

124

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