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TDA7505 Datasheet(PDF) 20 Page - STMicroelectronics |
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TDA7505 Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 38 page  Electrical specifications TDA7505 20/38 4.8 SPI interfaces (Buffered SPI, Display SPI, RDS SPI) Figure 6. SPI interfaces Table 14. SPI interfaces Symbol Description Min Typ Max Unit TDSP Internal DSP clock period (typical 1/75MHz) 13.33 ns Master mode tsclk Clock cycle 12 TDSP ns tdtr SCK edge to MOSI valid 40 ns tsetup MISO setup time 16 ns thold MISO hold time 9 ns tsclkh SCK high time 0.5 tsclk ns tsclkl SCK low time 0.5 tsclk ns tsssetup SS setup time 40 ns tsshold SS hold time 25 ns Slave mode tsclk Clock cycle 12 TDSP ns tdtr SCK edge to MOSI valid 40 ns tsetup MOSI setup time 16 ns thold MOSI hold time 9 ns tsclkh SCK high time 0.5 tsclk ns tsclkl SCK high low 0.5 tsclk ns tsssetup SS setup time 40 ns tsshold SS hold time 20 ns tsclk t sclkl tdtr tsssetup t setup t sclkh t hold tsshold Valid MIS O SS SCK Valid (CP O L=0,CPH A=0) MO S I |
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