TDA7505 datasheet(30/38 Pages) STMICROELECTRONICS

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Functional description

TDA7505

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5.2.5

I2C interface

The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter

IC control. The device is compliant with the I2C specification including the highs peed (400

kHz) mode.

Every component hooked up to the I2C bus has its own unique address whether it is a CPU,

memory or some other complex function chip. Each of these chips can act as a receiver and

/or transmitter on its functionality.

The device may act as master or as slave.

XCHG interface (DSP to DSP exchange interface)

The Exchange Interface peripheral provides bidirectional communication between DSP0

and DSP1. Both 24 bit word data and four bit Flag data can be exchanged. A FIFO is utilized

for received data. It minimizes the number of times an Exchange Interrupt Service Routine

would have to be called if multi-word blocks of data were to be received. The Transmit FIFO

is in effect the Receive FIFO of the other DSP and is written directly by the transmitting DSP.

The features of the XCHG are listed below:

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10 Word XCHG FIFO on DSP0 to transfer data to DSP1

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24 Word XCHG FIFO on DSP1 to transfer data to DSP0

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Four Flags for each XCHG for DSP to DSP signaling

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Condition flags can optionally trigger interrupts on both DSP´s

5.2.6

DRAM/SRAM interface (DEMI)

The External DRAM/SRAM Interface is viewed as a memory mapped peripheral of both

DSP cores. Data transfers are performed by moving data into/from data registers. The

control is exercised by polling status flags in the control/status register or by servicing

interrupts. This can be done by both DSP cores.

The features of the DEMI (Dual core Extended Memory Interface) are listed below:

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Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM

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Data word length 16 or 24 bits for DRAM

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Data word length 8 or 16 or 24 bits for SRAM

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13 DRAM address lines means 226 = 256M bit addressable DRAM

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Refresh rate for DRAM can be chosen among eight divider factors

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SRAM relative addressing mode; 222 = 32M bit addressable SRAM

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Four SRAM Timing choices

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Two Read Offset Registers

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