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TDA7505 Datasheet(PDF) 23 Page - STMicroelectronics |
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TDA7505 Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 38 page ![]() TDA7505 Electrical specifications 23/38 Figure 9. Debug port serial clock timing Figure 10. Debug port acknowledge timing Figure 11. Debug port data I/O to status timing 8 DBCK high to DBOUT invalid 3 ns 9 DBIN valid to DBCK low (set-up) 15 ns 10 DBCK low to DBIN invalid (hold) 3 ns DBOUT (ACK) asserted to first DBCK high 2*TDSP ns DBOUT (ACK) assertion width 5*TDSP - 3 5*TDSP + 7 ns 11 Last DBCK low of read register to first DBCK high of next command 7*TDSP + 10 ns 12 Last DBCK low to DBOUT invalid (hold) 3 ns DBSEL setup to DBCK TDSP ns Table 19. Debug port interface (continued) No. Characteristics (Fdsp = 75MHz) Min. Max. Unit (1) (3) (4) (5) (2) DBCK (input) D02AU1363 (6) DBRQN (input) DBOUT (output) D02AU1364 (ACK) (Last) DBCK (input) DBOUT (output) (9) (Note 1) Note: 1 High Impedance, external pull-down resistor DBIN (input) (10) D02AU1365 |
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