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TDA7505 Datasheet(PDF) 21 Page - STMicroelectronics |
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TDA7505 Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 38 page ![]() TDA7505 Electrical specifications 21/38 Figure 7. SPI clocking scheme 4.9 I2C Timing Figure 8. I2C Timing SCK SS (CPOL=0,CPHA=0) (CPOL=0,CPHA=1) (CPOL=1,CPHA=0) (CPOL=1,CPHA=1) SCK SCK SCK MSB 6 5 4 32 10 MISO MOSI Table 15. I2C Timing Symbol Parameter Test condition Standard mode I2C bus Fast mode I2C bus Unit Min. Max. Min. Max. FSCL SCLl clock frequency 0 100 0 400 kHz tBUF Bus free between a STOP and Start Condition 4.7 – 1.3 – ms tHD:STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 – 0.6 – ms tLOW LOW period of the SCL clock 4.7 – 1.3 – ms tHIGH HIGH period of the SCL clock 4.0 – 0.6 – ms tSU:STA Set-up time for a repeated start condition 4.7 – 0.6 – ms tHD:DAT DATA hold time 0 – 0 0.9 ms tR Rise time of both SDA and SCL signals Cb in pF – 1000 20+0.1Cb 300 ns |
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