BUF16821 datasheet(8/29 Pages) EPCOS

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APPLICATION INFORMATION

GENERAL

ADDRESSING THE BUF16821

TWO-WIRE BUS OVERVIEW

BUF16821

SBOS428 – JULY 2008 ...................................................................................................................................................................................................... www.ti.com

All slaves on the bus shift in the slave address byte

on the rising edge of SCL, with the last bit indicating

The BUF16821 programmable voltage reference

whether a read or write operation is intended. During

allows fast and easy adjustment of 16 programmable

the ninth clock pulse, the slave being addressed

gamma reference outputs and two VCOM outputs,

responds

the

master

generating

each

with

10-bit

resolution.

The

BUF16821

Acknowledge and pulling SDA LOW.

programmed through a high-speed, I2C interface. The

final gamma and VCOM values can be stored in the

Data transfer is then initiated and eight bits of data

onboard,

nonvolatile

memory.

allow

for

are sent, followed by an Acknowledge bit. During

programming errors or liquid crystal display (LCD)

data transfer, SDA must remain stable while SCL is

panel rework, the BUF16821 supports up to 16 write

HIGH. Any change in SDA while SCL is HIGH is

operations to the onboard memory. The BUF16821

interpreted as a START or STOP condition.

has

two

separate

memory

banks,

allowing

Once all data have been transferred, the master

simultaneous storage of two different gamma curves

generates a STOP condition, indicated by pulling

to facilitate dynamic switching between gamma

SDA from LOW to HIGH while SCL is HIGH. The

curves.

BUF16821 can act only as a slave device; therefore,

The BUF16821 can be powered using an analog

it never drives SCL. SCL is an input only for the

supply voltage from 9V to 20V, and a digital supply

BUF16821.

from 2V to 5.5V. The digital supply must be applied

before the analog supply to avoid excessive current

and power consumption, or possibly even damage to

The address of the BUF16821 is 111010x, where x is

the device if left connected only to the analog supply

the state of the A0 pin. When the A0 pin is LOW, the

for extended periods of time. Figure 10 illustrates a

device acknowledges on address 74h (1110100). If

typical configuration of the BUF16821.

the A0 pin is HIGH, the device acknowledges on

address 75h (1110101). Table 1 shows the A0 pin

settings and BUF16821 address options.

The

BUF16821

communicates

over

Other valid addresses are possible through a simple

industry-standard, two-wire interface to receive data

mask change. Contact your TI representative for

in slave mode. This standard uses a two-wire,

information.

open-drain interface that supports multiple devices on

a single bus. Bus lines are driven to a logic low level

Table 1. Quick-Reference of BUF16821 Addresses

only. The device that initiates the communication is

DEVICE/COMPONENT

called a master, and the devices controlled by the

master are slaves. The master generates the serial

BUF16821 Address

ADDRESS

clock on the clock signal line (SCL), controls the bus

A0 pin is LOW

1110100

access, and generates the START and STOP

(device acknowledges on address 74h)

conditions.

A0 pin is HIGH

1110101

(device acknowledges on address 75h)

To address a specific device, the master initiates a

START condition by pulling the data signal line (SDA)

from a HIGH to a LOW logic level while SCL is HIGH.

Table 2. Quick-Reference of Command Codes

COMMAND

CODE

General-Call Reset

Address byte of 00h followed by a data byte of 06h.

High-Speed Mode

00001xxx, with SCL

≤ 400kHz; where xxx are bits unique to the Hs-capable master. This

byte is called the Hs master code.

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