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32C82 Datasheet(PDF) 56 Page - Renesas Technology Corp |
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32C82 Datasheet(HTML) 56 Page - Renesas Technology Corp |
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56 / 82 page ![]() M32C/82 Group 5. Electrical Characteristics (VCC = 5V) 0 8 f o 4 0 0 2 , 1 0 . n u J 0 2 . 1 . v e R page 56 BCLK CSi 18ns.max ADi 18ns.max RD 18ns.max -5ns.min th(BCLK-AD) -3ns.min -3ns.min BHE ADi /DBi 0ns.min 18ns.max -3ns.min BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.min tcyc BHE ADi /DBi Data output WR,WRL, WRH Address Address Data input 26ns.min td(BCLK-RD) th(WR-CS)(1) Address td(AD-ALE)(1) Address tsu(DB-BCLK) tac3(RD-DB)(1) tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 18ns.max td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states) ALE 18ns.max -2ns.min td(BCLK-ALE) th(ALE-AD)(1) td(AD-ALE)=(tcyc/2-20)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min td(DB-WR)=(tcyc/2 x m-25)ns.min Vcc=5V td(BCLK-CS) td(AD-ALE)(1) th(ALE-AD)(1) th(BCLK-RD) th(RD-AD)(1) th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)(1) td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD)(1) td(DB-WR)(1) th(WR-DB)(1) th(BCLK-ALE) th(BCLK-ALE) tcyc NOTES: 1. It varies with the operation frequency. Measurement conditions • VCC=4.2 to 5.5V • Input high and low voltage: VIH=2.5V, VIL=0.8V • Output high and low voltage: VOH=2.0V, VOL=0.8V NOTES: 1. It varies with the operation frequency. Read timing Write timing (written in 2 cycles with no wait state) Memory expansion mode and microprocessor mode (with a wait state, when accessing an external memory and using the multiplexed bus) tac3(AD-DB)(1) Figure 5.4 VCC=5V Timing Diagram (3) |
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