4501 datasheet(109/116 Pages) RENESAS

109 / 116 page

4501 Group

Rev.3.01

2005.02.07

page 109 of 112

REJ03B0104-0301

Test conditions

Ta = 25 °C

RAM back-up mode

VDD = 5.0 V

(POF instruction execution) (Note 2)

Parameter

Detection voltage (Note 1)

Operation current of voltage

drop detection circuit

Symbol

VRST

IRST

Limits

Unit

Min.

2.7

3.3

Typ.

3.5

Max.

4.2

3.7

100

µA

Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs while the supply voltage (VDD) is falling.

2: The voltage drop detection circuit is operating in the RAM back-up with the POF instruction (It stops in the RAM back-up with the POF2 instruction).

XIN : high-speed mode

(System clock = f(XIN))

Parameter

Pin name

Machine cycle

MiMi+1

D0, D1, D2/C, D3/K

P00–P03

P10–P13

P00–P03

P10–P13

P20, P21

XIN : middle-speed mode

(System clock = f(XIN)/2)

P20, P21

Clock

Port D output

Port D input

Port P0, P1, P2

output

Port P0, P1, P2

input

CNTR

Timer output

XIN : low-speed mode

(System clock = f(XIN)/4)

XIN : default mode

(System clock = f(XIN)/8)

D0, D1, D2/C, D3/K

INT

Interrupt input

CNTR

Timer input

Basic timing diagram

Voltage drop detection circuit characteristics

(Ta = –20 °C to 85 °C, unless otherwise noted)

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