7513 datasheet(45/66 Pages) RENESAS

45 / 66 page

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

7513 Group

WATCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example, be-

cause of a software runaway).

The watchdog timer consists of an 8-bit watchdog timer L and a 6-

bit watchdog timer H. At reset or writing to the watchdog timer

control register (address 003716), the watchdog timer is set to

“3FFF16.” When any data is not written to the watchdog timer con-

trol register (address 003716) after reset, the watchdog timer is in

stop state. The watchdog timer starts to count down from “3FFF16”

by writing an optional value into the watchdog timer control regis-

ter (address 003716) and an internal reset occurs at an underflow.

Accordingly, programming is usually performed so that writing to

the watchdog timer control register (address 003716) may be

started before an underflow. The watchdog timer does not function

when an optional value has not been written to the watchdog timer

control register (address 003716). When address 003716 is read,

the following values are read:

qvalue of high-order 6-bit counter

qvalue of STP instruction disable bit

qvalue of count source selection bit.

When bit 6 of the watchdog timer control register (address 003716)

is set to “0,” the STP instruction is valid. The STP instruction is

disabled by rewriting this bit to “1.” At this time, if the STP instruc-

tion is executed, it is processed as an undefined instruction, so

that a reset occurs inside.

This bit cannot be rewritten to “0” by programming. This bit is “0”

immediately after reset.

The count source of the watchdog timer becomes the system

clock

φ divided by 8. The detection time in this case is set to 8.19 s

at f(XCIN) = 32 kHz and 65.536 ms at f(XIN) = 4 MHz.

However, count source of high-order 6-bit timer can be connected

to a signal divided system clock by 8 directly by writing the bit 7 of

the watchdog timer control register (address 003716) to “1.” The

detection time in this case is set to 32 ms at f(XCIN) = 32 kHz and

256

µs at f(XIN) = 4 MHz. There is no difference in the detection

time between the middle-speed mode and the high-speed mode.

Fig. 46 Block diagram of watchdog timer

Fig. 47 Structure of watchdog timer control register

Fig. 48 Timing of reset output

Internal

reset signal

Watchdog timer detection

≅ 2 ms (f(XIN) = 4 MHZ)

f(XIN)

XIN

Data bus

XCIN

“1”

“0”

Internal

system clock

selection bit

“0”

“1”

1/16

Watchdog timer count

source selection bit

Reset circuit

Undefined instruction

Reset

“3F16” is set when

watchdog timer is

written to.

Internal reset

RESETIN

Reset release time wait

“FF16” is set when

watchdog timer is

written to.

STP instruction

STP instruction disable bit

Watchdog timer

H (6)

Watchdog timer

L (8)

Watchdog timer register (address 003716)

WDTCON

STP instruction disable bit

0 : STP instruction enabled

1 : STP instruction disabled

Watchdog timer H count source selecion bit

0 : Internal system clock/2048 (f(XIN)/4096)

1 : Internal system clock/8 (f(XIN)/16)

Watchdog timer H (for read-out of high-order 6 bit)

“3FFF16” is set to the watchdog timer by writing values to this address.

7513 Datasheet(PDF) 45 Page - Renesas Technology Corp

7513 Datasheet(HTML) 45 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL