7513 datasheet(23/66 Pages) RENESAS

23 / 66 page

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

7513 Group

Fig. 16 Interrupt control

Fig. 17 Structure of interrupt-related registers

Interrupt edge selection register

INT0 interrupt edge selection bit

INT1 interrupt edge selection bit

INT2 interrupt edge selection bit

ADT interrupt edge selection bit

Not used (return “0” when read)

(INTEDGE : address 003A16)

Interrupt request register 1

INT0 interrupt request bit

INT1 interrupt request bit

Serial I/O1 receive interrupt request bit

Serial I/O1 transmit interrupt request bit

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 2 interrupt request bit

Timer 3 interrupt request bit

Interrupt control register 1

INT0 interrupt enable bit

INT1 interrupt enable bit

Serial I/O1 receive interrupt enable bit

Serial I/O1 transmit interrupt enable bit

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 2 interrupt enable bit

Timer 3 interrupt enable bit

0 : No interrupt request issued

1 : Interrupt request issued

(IREQ1 : address 003C16)

(ICON1 : address 003E16)

Interrupt request register 2

CNTR0 interrupt request bit

CNTR1 interrupt request bit

Timer 1 interrupt request bit

INT2 interrupt request bit

Serial I/O2 interrupt request bit

Key input interrupt request bit

ADT/AD conversion interrupt request bit

Not used (returns “0” when read)

(IREQ2 : address 003D16)

Interrupt control register 2

CNTR0 interrupt enable bit

CNTR1 interrupt enable bit

Timer 1 interrupt enable bit

INT2 interrupt enable bit

Serial I/O2 interrupt enable bit

Key input interrupt enable bit

ADT/AD conversion interrupt enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit.)

0 : Interrupts disabled

1 : Interrupts enabled

(ICON2 : address 003F16)

0 : Falling edge active

1 : Rising edge active

Key input control register

P20 trigger valid bit

P21 trigger valid bit

P22 trigger valid bit

P23 trigger valid bit

P24 trigger valid bit

P25 trigger valid bit

P26 trigger valid bit

P27 trigger valid bit

0 : Trigger invalid

1 : Trigger valid

(KIC : address 001516)

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

BRK instruction

Reset

Interrupt request

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

➀ Set the corresponding interrupt enable bit to “0” (disabled).

➁ Set the interrupt edge selection bit (active edge switch bit) or

the interrupt source selection bit to “1”.

➂ Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

➃ Set the corresponding interrupt enable bit to “1” (enabled).

7513 Datasheet(PDF) 23 Page - Renesas Technology Corp

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