7513 datasheet(22/66 Pages) RENESAS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

7513 Group

INTERRUPTS

Interrupts occur by seventeen sources: seven external, nine inter-

nal, and one software.

Interrupt Control

Each interrupt except the BRK instruction interrupt has both an in-

terrupt request bit and an interrupt enable bit, and is controlled by

the interrupt disable flag. An interrupt occurs if the corresponding

interrupt request and enable bits are “1” and the interrupt disable

flag is “0”. Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software. The BRK instruction interrupt and reset cannot be

disabled with any flag or bit. The I flag disables all interrupts ex-

cept the BRK instruction interrupt and reset. If several interrupts

requests occurs at the same time, the interrupt with highest prior-

ity is accepted first.

Interrupt Operation

Upon acceptance of an interrupt the following operations are auto-

matically performed:

1. The contents of the program counter and processor status

2. The interrupt disable flag is set and the corresponding

interrupt request bit is cleared.

3. The interrupt jump destination address is read from the vec-

tor table into the program counter.

sNotes

When setting the followings, the interrupt request bit may be set to

“1”.

•When setting external interrupt active edge

Related register: Interrupt edge selection register (address 3A16)

Timer X mode register (address 2716)

Timer Y mode register (address 2816)

•When switching interrupt sources of an interrupt vector address

where two or more interrupt sources are allocated

Related register: A-D control register (address 003116)

Notes1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Table 8 Interrupt vector addresses and priority

Remarks

Interrupt Request

Generating Conditions

At reset

At detection of either rising or

falling edge of INT0 input

At detection of either rising or

falling edge of INT1 input

At completion of serial I/O1 data

reception

At completion of serial I/O1

transmit shift or when transmis-

sion buffer is empty

Interrupt Source

Low

High

Priority

Vector Addresses (Note 1)

Reset (Note 2)

INT0

INT1

Serial I/O1

reception

Serial I/O1

transmission

Timer X

Timer Y

Timer 2

Timer 3

CNTR0

CNTR1

Timer 1

INT2

Serial I/O2

Key input

(Key-on wake-up)

ADT

A-D conversion

BRK instruction

FFFD16

FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116

FFEF16

FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116

FFDF16

FFDD16

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16

FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016

FFDE16

FFDC16

At timer X underflow

At timer Y underflow

At timer 2 underflow

At timer 3 underflow

At detection of either rising or

falling edge of CNTR0 input

At detection of either rising or

falling edge of CNTR1 input

At timer 1 underflow

At detection of either rising or

falling edge of INT2 input

At completion of serial I/O2 data

transmission or reception

At falling of conjunction of input

level for port P2 (at input mode)

At either rising or falling edge of

ADT input

At completion of A-D conversion

At BRK instruction execution

Non-maskable

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O1 is selected

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

External interrupt

(active edge selectable)

Valid when serial I/O2 is selected

External interrupt

(valid at falling)

External interrupt (Valid when ADT

interrupt is selected

Valid when A-D interrupt is se-

lected

Non-maskable software interrupt

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