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M61283FP Datasheet(PDF) 29 Page - Renesas Technology Corp |
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M61283FP Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 55 page ![]() M61283FP Rev.1.0, Sep.23.2003, page 29 of 54 CRF2 chroma trap attenuation 2 (normal R/G/B output) 1. Input SG.L to pin 46. The input 3.58 MHz frequency level is N 1. 2. Measure the 3.58 MHz frequency level when TRAP ON/OFF (07H D3) DATA 0. 3. CRF2 is defined as follows. YDL1: YDL time 1 1. Input SG.A to pin 46. 2. Measure the delay time relative to the input signal of pins 14, 15, 16. The delay time at 50% rise level is measured. YDL2, 3, 4: YDL time 2, 3, 4 1. Input SG.A to pin 46. 2. Measure the delay time of the input signal and the pin 14, 15, 16 output signals. 3. YDL2, YDL3, YDL4 are defined as follows. YDL2 = measured value (ns) – YDL1 (measured value) YDL3 = measured value (ns) – YDL2 (measured value) YDL4 = measured value (ns) – YDL3 (measured value) DLYO1: DELAYED YOUT time 1 1. Input SG.A to pin 46. 2. Measure the delay time relative to the input signal of pin 58. The delay time at 50% rise level is measured. DLYO2,3,4: DELAYED YOUT time 2, 3, 4 1. Input SG.A to pin 46. 2. Measure the delay time of the input signal and the pin 58 output signal. 3. DLYO2, DLYO3, DLYO4 are defined as follows. DLYO2 = measured value (ns) - DLYO1 (measured value) DLYO3 = measured value (ns) - DLYO2 (measured value) DLYO4 = measured value (ns) - DLYO3 (measured value) |
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