| Electronic Components Datasheet Search |
|
M61558FP Datasheet(PDF) 7 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M61558FP Datasheet(HTML) 7 Page - Renesas Technology Corp |
|
7 / 18 page ![]() M61558FP Rev.1.0, Sep.19.2003, page 7 of 17 Layer 1 (surface) Layer 2 (rear) *1 Thermal derating characteristics measured for the board specified by Renesas (Board specifications) Material: Glass epoxy FR-4 Dimensions: 70 × 70 mm Thickness: t = 1.6 mm (Wiring specifications for layers 1 and 2) Material: Copper Thickness: t = 18 mm Precautions on Usage 1. This product radiates heat even during normal operation, and reaches high temperatures. There is a possibility that characteristics failure or breakdown, including in peripheral components and circuits, may cause this product or peripherals to reach abnormally high temperatures. Also, please take special care when using this product as the final stage, since it may then be susceptible to damage because of external factors. This product is designed for consumer applications. Accordingly, please use it within the specified thermal conditions. Usage of the product in more relaxed thermal conditions may lead to malfunctions or damage to the product. 2. This product incorporates an over-current protection circuit which terminates the PWM operation when the peak instantaneous current from the VDA or the VDB power supply exceeds 7.5 A (designed value). Please note that it is never required to supply more current than this. The maximum-current value is roughly below 3 A during operation with a standard 4- Ω load. In usage, care is required with regard to the stability of the power-supply voltage. 3. Detection of an abnormality (when the PROUT pin (pin 21) becomes low) indicates a possibility of over current, so eliminate the cause, such as shorting of the output pins, and release the IC from the protection state (input low level on the EN pin (pin 25)). 4. This product includes MOS FET and CMOS logic circuits. Accordingly, electrostatic break down or latch-up may be generated within these elements. Please take the same care in using this product as in any case where MOS FET and CMOS logic LSIs are in use. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |