M61558FP

Rev.1.0, Sep.19.2003, page 8 of 17

Recommended Operating Condition

Limits

Item

Symbol

Min.

Typ.

Max.

Unit

Condition

VD power-supply voltage

VD

16

21

24

V

VDA (pins 5, 6), VDB (pins 37, 38)

VDD power-supply voltage

VDD

10.8

12.0

13.2

V

VDDA (pin 12), VDDB (pin 30), VDDP

(pin 20)

PWM frequency

fpwm

0.7

1.5

MHz

INA+ (pin 17), INB+ (pin 26)

Min. operating pulse width

Tpw MIN

40





ns

INA+ (pin 17), INB+ (pin 26)

High input voltage

VinH

4.0



5.0

V

INA+ (pin 17), INB+ (pin 26)

Low input voltage

VinL

0.0



0.8

V

INA+ (pin 17), INB+ (pin 26), EN (pin 25)

Notes:

1. PWM operation

Do not input a signal shorter than the minimum pulse width, since this may lead to unstable operation or, in the

worst case, damage to the product. Since boot-strap operation is performed, an input signal with aperiodical high

and low levels may lead to abnormal operation. Ensure that the PWM signal has periodical high and low levels. The

capacitance of the capacitor for boot-strapping in the sample application diagram is for the product in operation at

768 kHz. The thermal conditions, etc., become looser with operation at lower PWM frequencies.

2. Power-supply voltage

The normal operating condition for this product is VDD voltage < VD voltage, so ensure that this is the state during

normal operation. Setting a lower VDD voltage increases the margin against damage but carries the danger of the

under voltage detection circuit malfunctioning, so please ensure that VDD is maintained at 9 V or more.

3. Mounting (board)

The board layout must be capable of handling the same high frequencies and high levels of power as are handled by

this IC. Furthermore, components must be selected in consideration of both audio-frequency and high-frequency

characteristics. Please external note that large surges are generated by parasitic inductances during high-speed

switching. This IC is designed specifically for bridge-tied load (BTL) operation, so the design focus was on

symmetry of sides A and B. The pattern on the board must also be highly symmetrical for BTL configuration.