SH7261 datasheet(450/1348 Pages) RENESAS

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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 418 of 1312

REJ09B0320-0200

12.3.6

Timer Status Register (TSR)

The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The

MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5.

• TSR_0, TSR_1, TSR_2, TSR_3, TSR_4

Bit:

Initial value:

R/W:

7654321

11000000

R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*

Note:

Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

TCFD

—

TCFU TCFV TGFD TGFC TGFB TGFA

111111

Bit

Bit Name

Initial

Value

R/W

Description

TCFD

Count Direction Flag

Status flag that shows the direction in which TCNT

counts in channels 1 to 4.

In channel 0, bit 7 is reserved. It is always read as 1

and the write value should always be 1.

0: TCNT counts down

1: TCNT counts up

—

Reserved

This bit is always read as 1. The write value should

always be 1.

TCFU

R/(W)*

Underflow Flag

Status flag that indicates that TCNT underflow has

occurred when channels 1 and 2 are set to phase

counting mode. Only 0 can be written, for flag clearing.

In channels 0, 3, and 4, bit 5 is reserved. It is always

read as 0 and the write value should always be 0.

[Setting condition]

• When the TCNT value underflows (changes from

H'0000 to H'FFFF)

[Clearing condition]

• When 0 is written to TCFU after reading TCFU = 1*2

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