SH7261 datasheet(454/1348 Pages) RENESAS

454 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 422 of 1312

REJ09B0320-0200

• TSR2_0

Bit:

Initial value:

R/W:

7654321

11000000

RRRRRR

Note:

Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

——————

TGFF TGFE

R/(W)* R/(W)*

Bit

Bit Name

Initial

Value

R/W

Description

7, 6

—

All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

5 to 2

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TGFF

R/(W)*

Compare Match Flag F

Status flag that indicates the occurrence of compare

match between TCNT_0 and TGRF_0.

[Setting condition]

• When TCNT_0 = TGRF_0 and TGRF_0 is

functioning as compare register

[Clearing condition]

• When 0 is written to TGFF after reading

TGFF = 1*

TGFE

R/(W)*

Compare Match Flag E

Status flag that indicates the occurrence of compare

match between TCNT_0 and TGRE_0.

[Setting condition]

• When TCNT_0 = TGRE_0 and TGRE_0 is

functioning as compare register

[Clearing condition]

• When 0 is written to TGFE after reading

TGFE = 1*

Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after

reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is

held.

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