SH7261 datasheet(458/1348 Pages) RENESAS

458 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 426 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

TTSA

R/W

Timing Select A

Specifies the timing for transferring data from TGRC to

TGRA in each channel when they are used together for

buffer operation.

Do not set this bit to 1 when the channel is to be used

in a mode other than PWM mode.

0: When compare match A occurs in each channel

1: When TCNT is cleared in each channel

12.3.8

Timer Input Capture Control Register (TICCR)

TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1

and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.

Bit:

Initial value:

R/W:

7654321

00000000

R/W

—

I2BE

I2AE

I1BE

I1AE

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

I2BE

R/W

Input Capture Enable

Specifies whether to include the TIOC2B pin in the

TGRB_1 input capture conditions.

0: Does not include the TIOC2B pin in the TGRB_1

input capture conditions

1: Includes the TIOC2B pin in the TGRB_1 input

capture conditions

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