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SH7261 Datasheet(PDF) 462 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 462 Page - Renesas Technology Corp |
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462 / 1348 page  Section 12 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 Sep. 07, 2007 Page 430 of 1312 REJ09B0320-0200 Table 12.29 Setting of Transfer Timing by BF1 and BF0 Bits Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register. 0 1 Transfers data from the cycle set buffer register to the cycle set register at the crest of the TCNT_4 count.* 1 1 0 Transfers data from the cycle set buffer register to the cycle set register at the trough of the TCNT_4 count.* 2 1 1 Transfers data from the cycle set buffer register to the cycle set register at the crest and trough of the TCNT_4 count.* 2 Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected. 12.3.10 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. |
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