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SH7261 Datasheet(PDF) 461 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 461 Page - Renesas Technology Corp

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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 429 of 1312
REJ09B0320-0200
Bit
Bit Name
Initial
Value
R/W
Description
4
DT4BE
0*
R/W
Down-Count TRG4BN Enable
Enables or disables A/D converter start requests
(TRG4BN) during TCNT_4 down-count operation.
0: A/D converter start requests (TRG4BN) disabled
during TCNT_4 down-count operation
1: A/D converter start requests (TRG4BN) enabled
during TCNT_4 down-count operation
3
ITA3AE
0*
R/W
TGIA_3 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4AN) with TGIA_3 interrupt skipping operation.
0: Does not link with TGIA_3 interrupt skipping
1: Links with TGIA_3 interrupt skipping
2
ITA4VE
0*
R/W
TCIV_4 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4AN) with TCIV_4 interrupt skipping operation.
0: Does not link with TCIV_4 interrupt skipping
1: Links with TCIV_4 interrupt skipping
1
ITB3AE
0*
R/W
TGIA_3 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4BN) with TGIA_3 interrupt skipping operation.
0: Does not link with TGIA_3 interrupt skipping
1: Links with TGIA_3 interrupt skipping
0
ITB4VE
0*
R/W
TCIV_4 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4BN) with TCIV_4 interrupt skipping operation.
0: Does not link with TCIV_4 interrupt skipping
1: Links with TCIV_4 interrupt skipping
Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits.
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR
and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with
interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the
timer A/D converter start request control register (TADCR) to 0).
3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D
converter start requests will not be issued.
*
Do not set to 1 when complementary PWM mode is not selected.



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