SH7261 datasheet(459/1348 Pages) RENESAS

459 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 427 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

I2AE

R/W

Input Capture Enable

Specifies whether to include the TIOC2A pin in the

TGRA_1 input capture conditions.

0: Does not include the TIOC2A pin in the TGRA_1

input capture conditions

1: Includes the TIOC2A pin in the TGRA_1 input

capture conditions

I1BE

R/W

Input Capture Enable

Specifies whether to include the TIOC1B pin in the

TGRB_2 input capture conditions.

0: Does not include the TIOC1B pin in the TGRB_2

input capture conditions

1: Includes the TIOC1B pin in the TGRB_2 input

capture conditions

I1AE

R/W

Input Capture Enable

Specifies whether to include the TIOC1A pin in the

TGRA_2 input capture conditions.

0: Does not include the TIOC1A pin in the TGRA_2

input capture conditions

1: Includes the TIOC1A pin in the TGRA_2 input

capture conditions

12.3.9

Timer A/D Converter Start Request Control Register (TADCR)

TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests

and specifies whether to link A/D converter start requests with interrupt skipping operation. The

MTU2 has one TADCR in channel 4.

Bit:

Initial value:

R/W:

000000000

00*

R/W

Note:

Do not set to 1 when complementary PWM mode is not selected.

BF[1:0]

—

UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE

SH7261 Datasheet(PDF) 459 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 459 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL