Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SH7261 Datasheet(PDF) 451 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 451 Page - Renesas Technology Corp

Back Button SH7261 Datasheet HTML 447Page - Renesas Technology Corp SH7261 Datasheet HTML 448Page - Renesas Technology Corp SH7261 Datasheet HTML 449Page - Renesas Technology Corp SH7261 Datasheet HTML 450Page - Renesas Technology Corp SH7261 Datasheet HTML 451Page - Renesas Technology Corp SH7261 Datasheet HTML 452Page - Renesas Technology Corp SH7261 Datasheet HTML 453Page - Renesas Technology Corp SH7261 Datasheet HTML 454Page - Renesas Technology Corp SH7261 Datasheet HTML 455Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 451 / 1348 page
background image
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 419 of 1312
REJ09B0320-0200
Bit
Bit Name
Initial
Value
R/W
Description
4
TCFV
0
R/(W)*
1
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Setting condition]
• When the TCNT value overflows (changes from
H'FFFF to H'0000)
In channel 4, when the TCNT_4 value underflows
(changes from H'0001 to H'0000) in complementary
PWM mode, this flag is also set.
[Clearing condition]
• When 0 is written to TCFV after reading
TCFV = 1*
2
3
TGFD
0
R/(W)*
1
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0, 3, and 4.
Only 0 can be written, for flag clearing. In channels 1
and 2, bit 3 is reserved. It is always read as 0 and the
write value should always be 0.
[Setting conditions]
• When TCNT = TGRD and TGRD is functioning as
output compare register
• When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
[Clearing condition]
• When 0 is written to TGFD after reading
TGFD = 1*
2



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com