SH7261 datasheet(526/1348 Pages) RENESAS

526 / 1348 page

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 Sep. 07, 2007 Page 494 of 1312

REJ09B0320-0200

Table 12.55 Register Settings for Complementary PWM Mode

Channel

Counter/Register

Description

Read/Write from CPU

TCNT_3

Start of up-count from value set

in dead time register

Maskable by TRWER

setting*

TGRA_3

Set TCNT_3 upper limit value

(1/2 carrier cycle + dead time)

Maskable by TRWER

setting*

TGRB_3

PWM output 1 compare register

Maskable by TRWER

setting*

TGRC_3

TGRA_3 buffer register

Always readable/writable

TGRD_3

PWM output 1/TGRB_3 buffer

Always readable/writable

TCNT_4

Up-count start, initialized to

H'0000

Maskable by TRWER

setting*

TGRA_4

PWM output 2 compare register

Maskable by TRWER

setting*

TGRB_4

PWM output 3 compare register

Maskable by TRWER

setting*

TGRC_4

PWM output 2/TGRA_4 buffer

Always readable/writable

TGRD_4

PWM output 3/TGRB_4 buffer

Always readable/writable

Timer dead time data register

(TDDR)

Set TCNT_4 and TCNT_3 offset

value (dead time value)

Maskable by TRWER

setting*

Timer cycle data register

(TCDR)

Set TCNT_4 upper limit value

(1/2 carrier cycle)

Maskable by TRWER

setting*

Timer cycle buffer register

(TCBR)

TCDR buffer register

Always readable/writable

Subcounter (TCNTS)

Subcounter for dead time

generation

Read-only

Temporary register 1 (TEMP1)

PWM output 1/TGRB_3

temporary register

Not readable/writable

Temporary register 2 (TEMP2)

PWM output 2/TGRA_4

temporary register

Not readable/writable

Temporary register 3 (TEMP3)

PWM output 3/TGRB_4

temporary register

Not readable/writable

Note:

Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER

(timer read/write enable register).

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