SH7261 datasheet(785/1348 Pages) RENESAS

785 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 753 of 1312

REJ09B0320-0200

RDRF

RCVD

ICDRS

ICDRR

AA/

Data n-1

Data n

Data n-1

[5] Read ICDRR after setting RCVD

[6] Issue stop

condition

[7] Read ICDRR,

and clear RCVD

[8] Set slave

receive mode

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

User

processing

Figure 17.8 Master Receive Mode Operation Timing (2)

17.4.4

Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs

the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,

refer to figures 17.9 and 17.10.

The transmission procedure and operations in slave transmit mode are described below.

1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and

TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches.

2. When the slave address matches in the first frame following detection of the start condition,

the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th

clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS bit in ICCR1 and the TDRE bit

in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The

continuous transmission is performed by writing transmit data to ICDRT every time TDRE is

set.

3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,

with TDRE = 1. When TEND is set, clear TEND.

4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is opened.

5. Clear TDRE.

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