SH7261 datasheet(789/1348 Pages) RENESAS

789 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 757 of 1312

REJ09B0320-0200

ICDRS

ICDRR

RDRF

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

SCL

(Slave output)

User

processing

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Data 1

[3] Set ACKBT

[3] Read ICDRR

[4] Read ICDRR

Data 2

Data 1

Figure 17.12 Slave Receive Mode Operation Timing (2)

17.4.6

Clocked Synchronous Serial Format

This module can be operated with the clocked synchronous serial format, by setting the FS bit in

SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When

MST is 0, the external clock input is selected.

(1)

Data Transfer Format

Figure 17.13 shows the clocked synchronous serial transfer format.

The transfer data is output from the fall to the fall of the SCL clock, and the data at the rising edge

of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the

MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the

SDAO bit in ICCR2.

SDA

SCL

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5 Bit 6

Bit 7

Figure 17.13 Clocked Synchronous Serial Transfer Format

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