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SH7261 Datasheet(PDF) 790 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 790 Page - Renesas Technology Corp

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Section 17 I
2C Bus Interface 3 (IIC3)
Rev. 2.00 Sep. 07, 2007 Page 758 of 1312
REJ09B0320-0200
(2)
Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For
transmit mode operation timing, refer to figure 17.14. The transmission procedure and operations
in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS[3:0] bits in ICCR1. (Initial setting)
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
12
7
8
1
7
8
1
SCL
TRS
TDRE
ICDRT
ICDRS
Bit 0
Data 1
Data 1
Data 2
Data 3
Data 3
Data 2
Bit 6
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
Bit 1
SDA
(Output)
User
processing
[3] Write data
to ICDRT
[3] Write data
to ICDRT
[3] Write data
to ICDRT
[3] Write data
to ICDRT
[2] Set TRS
Figure 17.14 Transmit Mode Operation Timing



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