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SH7261 Datasheet(PDF) 792 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 792 Page - Renesas Technology Corp |
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792 / 1348 page ![]() Section 17 I 2C Bus Interface 3 (IIC3) Rev. 2.00 Sep. 07, 2007 Page 760 of 1312 REJ09B0320-0200 12 7 8 1 7 8 1 2 SCL MST TRS RDRF ICDRS ICDRR SDA (Input) Bit 0 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 Bit 1 User processing Data 1 Data 1 Data 2 Data 2 Data 3 [2] Set MST (when outputting the clock) [3] Read ICDRR [3] Read ICDRR Figure 17.15 Receive Mode Operation Timing 12 3 4 5 6 7 8 000 SCL MST RCVD 111 110 101 100 011 010 001 000 SDA (Input) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 BC2 to BC0 [2] Set MST [3] Set the RCVD bit after checking if BC2 = 1 Figure 17.16 Operation Timing For Receiving One Byte (MST = 1) |
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