SH7261 datasheet(793/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

793 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 761 of 1312

REJ09B0320-0200

17.4.7

Noise Filter

The logic levels at the SCL and SDA pins are routed through noise filters before being latched

internally. Figure 17.17 shows a block diagram of the noise filter circuit.

The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input

signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed

forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this

signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do

not agree, the previous value is held.

NF2CYC

SCL or SDA

input signal

Internal

SCL or SDA

signal

Sampling clock

Sampling

clock

Peripheral clock

cycle

Latch

Match

detector

Latch

Match

detector

Figure 17.17 Block Diagram of Noise Filter

SH7261 Datasheet(PDF) 793 Page - Renesas Technology Corp