SH7261 datasheet(797/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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797 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 765 of 1312

REJ09B0320-0200

Yes

RDRF = 1 ?

Yes

RDRF = 1 ?

Last receive - 1?

Slave receive mode

Clear AAS in ICSR

Clear ACKBT in ICIER to 0

Dummy-read ICDRR

Read RDRF in ICSR

Read ICDRR

Set ACKBT in ICIER to 1

Read ICDRR

Read RDRF in ICSR

Read ICDRR

End

Yes

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[1] Clear the AAS flag.

[2] Set acknowledge to the transmit device.

[3] Dummy-read ICDRR.

[4] Wait for 1 byte to be received.

[5] Check whether it is the (last receive - 1).

[6] Read the receive data.

[7] Set acknowledge of the last byte.

[8] Read the (last byte - 1) of receive data.

[9] Wait the last byte to be received.

[10] Read for the last byte of receive data.

Note: When the size of receive data is only one byte in

reception, steps [2] to [6] are skipped after

step [1], before jumping to step [7]. The step [8]

is dummy-read in ICDRR.

Figure 17.21 Sample Flowchart for Slave Receive Mode

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