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SH7261 Datasheet(PDF) 800 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 800 Page - Renesas Technology Corp

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Section 17 I
2C Bus Interface 3 (IIC3)
Rev. 2.00 Sep. 07, 2007 Page 768 of 1312
REJ09B0320-0200
V
IH
V
IH
V
IH
V
IH
(1) Normal case
Synchronous
clock*1
SCL pin
Slave low
level output
Internal delay*2
Monitored value is high level
Monitored value
is high level
Monitored value
is high level
Internally
monitored SCL
(2) When SCL is driven low at first by the slave device
Synchronous
clock*1
SCL pin
Monitored value
is low level
Monitored value
is low level
Internally
monitored SCL
(3) When the rising speed of SCL is slow
Synchronous
clock*1
SCL pin
Notes: 1. Clock whose transfer rate is set by bits CKS[3:0] in I2C bus control register 1 (ICCR1).
2. 3 to 4 t
pcyc when the NF2CYC bit in NF2CYC is 0 and 4 to 5 tpcyc when the NF2CYC bit is 1.
The rate is slower
than the settings.
Internally
monitored SCL
Time for
monitoring SCL
Time for
monitoring SCL
Time for
monitoring SCL
Time for
monitoring SCL
Time for
monitoring SCL
Internal delay*2
Internal delay*2
SCL not driven to low level
SCL not driven
to low level
Internal delay*2
Figure 17.22 Bit Synchronous Circuit Timing



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