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SH7261 Datasheet(PDF) 799 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 799 Page - Renesas Technology Corp |
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799 / 1348 page ![]() Section 17 I 2C Bus Interface 3 (IIC3) Rev. 2.00 Sep. 07, 2007 Page 767 of 1312 REJ09B0320-0200 17.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull- up resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 17.22 shows the timing of the bit synchronous circuit and table 17.5 shows the time when the SCL output changes from low to Hi-Z then SCL is monitored. |
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