SH7261 datasheet(798/1348 Pages) RENESAS

798 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 766 of 1312

REJ09B0320-0200

17.5

Interrupt Requests

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,

NACK detection, STOP recognition, and arbitration lost/overrun error. Table 17.4 shows the

contents of each interrupt request.

Table 17.4

Interrupt Requests

Interrupt Request

Abbreviation

Interrupt Condition

2C Bus

Format

Clocked Synchronous

Serial Format

Transmit data Empty

TXI

(TDRE = 1)

• (TIE = 1)

√

Transmit end

TEI

(TEND = 1)

• (TEIE = 1)

√

Receive data full

RXI

(RDRF = 1)

• (RIE = 1)

√

STOP recognition

STPI

(STOP = 1)

• (STIE = 1)

√



NACK detection

√



Arbitration lost/

overrun error

NAKI

{(NACKF = 1) + (AL = 1)}

•

(NAKIE = 1)

√

When the interrupt condition described in table 17.4 is 1, the CPU executes an interrupt exception

handling. Note that a TXI or RXI interrupt can activate the DMAC if the setting for DMAC

activation has been made. In such a case, an interrupt request is not sent to the CPU. Interrupt

sources should be cleared in the exception handling. The TDRE and TEND bits are automatically

cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is automatically cleared to 0 by

reading ICDRR. The TDRE bit is set to 1 again at the same time when the transmit data is written

to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an excessive data of one byte may

be transmitted.

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