SH7261 datasheet(802/1348 Pages) RENESAS

802 / 1348 page

Section 17 I

2C Bus Interface 3 (IIC3)

Rev. 2.00 Sep. 07, 2007 Page 770 of 1312

REJ09B0320-0200

17.7

Usage Note

17.7.1

Issuance of Stop Condition and Start Condition (Retransmission)

Issue a start (retransmission) or stop condition after the falling edge of the 9th clock has been

recognized. The falling edge of the 9th clock can be recognized by checking the SCLO bit in the

2C bus control register 2 (ICCR2). When a start (retransmission) or stop condition is issued with a

certain timing under the following conditions (1 or 2), the start (retransmission) or stop condition

may not be output correctly. Usage under conditions other than those described below will not

cause any problem.

1. SCL takes longer to rise than the period defined in section 17.6, Bit Synchronous Circuit, due

to the load of the SCL bus (load capacitance or pull-up resistance).

2. The low-level period between the 8th and 9th clock is prolonged by the slave device, which

activates the bit synchronous circuit.

17.7.2

Settings for Multi-Master Operation

1. Transfer rate setting

In multi-master operation, specify a transfer rate of at least 1/1.8 of the fastest transfer rate

among the other masters. For example, when the fastest of the other masters is at 400 kbps, the

IIC transfer rate of this LSI must be specified as 223 kbps (= 400/1.8) or a higher rate.

2. MST and TRS bits in ICCR1

In multi-master operation, use the MOV instruction to set the MST and TRS bits in ICCR1.

3. Loss of arbitration

When arbitration is lost, check whether the MST and TRS bits in ICCR1 are 0. If the MST and

TRS bits in ICCR1 have been set to a value other than 0, clear the bits to 0.

17.7.3

Reading ICDRR in Master Receive Mode

In master receive mode, read ICDRR before the rising edge of the 8th clock of SCL. If ICDRR

cannot be read before the rising edge of the 8th clock so that the next round of reception proceeds

with the RDRF bit in ICSR set to 1, the 8the clock is fixed low and the 9th clock is output.

If ICDRR cannot be read before the rising edge of the 8th clock of SCL, set the RCVD bit in

ICRR1 to 1 so that transfer proceeds in byte units.

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